|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10647 case MCK_ZPRExtendUXTW6464: {
12189 case MCK_ZPRExtendUXTW6464: return "MCK_ZPRExtendUXTW6464";
12799 { 88 /* adr */, AArch64::ADR_UXTW_ZZZ_D_3, Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64641_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK__91_, MCK_SVEVectorDReg, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
14975 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
14983 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
15809 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
15817 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
16866 { 3673 /* prfd */, AArch64::PRFD_D_UXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
18310 { 5243 /* st1d */, AArch64::SST1D_UXTW_SCALED, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
18318 { 5243 /* st1d */, AArch64::SST1D_UXTW_SCALED, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
20157 { 88 /* adr */, AArch64::ADR_UXTW_ZZZ_D_3, Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendUXTW64641_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK__91_, MCK_SVEVectorDReg, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
22333 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
22341 { 1863 /* ld1d */, AArch64::GLD1D_UXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
23167 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
23175 { 2457 /* ldff1d */, AArch64::GLDFF1D_UXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
24224 { 3673 /* prfd */, AArch64::PRFD_D_UXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
25668 { 5243 /* st1d */, AArch64::SST1D_UXTW_SCALED, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
25676 { 5243 /* st1d */, AArch64::SST1D_UXTW_SCALED, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW6464, MCK__93_ }, },
27806 { 88 /* adr */, 8 /* 3 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
27808 { 88 /* adr */, 8 /* 3 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
31257 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
31260 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
31303 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
31306 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
33101 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
33104 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
33147 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
33150 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
35520 { 3673 /* prfd */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
35523 { 3673 /* prfd */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
37913 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
37916 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
37959 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
37962 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendUXTW6464, AMFBS_HasSVE },
40779 case MCK_ZPRExtendUXTW6464: