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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10503 case MCK_ZPRExtendUXTW3216: {
12173 case MCK_ZPRExtendUXTW3216: return "MCK_ZPRExtendUXTW3216";
15002 { 1868 /* ld1h */, AArch64::GLD1H_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15017 { 1868 /* ld1h */, AArch64::GLD1H_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15217 { 1957 /* ld1sh */, AArch64::GLD1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15231 { 1957 /* ld1sh */, AArch64::GLD1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15834 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15849 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15901 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
15915 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
16875 { 3678 /* prfh */, AArch64::PRFH_S_UXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
18337 { 5248 /* st1h */, AArch64::SST1H_S_UXTW_SCALED, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
18352 { 5248 /* st1h */, AArch64::SST1H_S_UXTW_SCALED, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
22360 { 1868 /* ld1h */, AArch64::GLD1H_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
22375 { 1868 /* ld1h */, AArch64::GLD1H_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
22575 { 1957 /* ld1sh */, AArch64::GLD1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
22589 { 1957 /* ld1sh */, AArch64::GLD1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
23192 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
23207 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
23259 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
23273 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_UXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendUXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
24233 { 3678 /* prfh */, AArch64::PRFH_S_UXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
25695 { 5248 /* st1h */, AArch64::SST1H_S_UXTW_SCALED, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
25710 { 5248 /* st1h */, AArch64::SST1H_S_UXTW_SCALED, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendUXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendUXTW3216, MCK__93_ }, },
31397 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
31400 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
31483 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
31486 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
32179 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
32182 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
32259 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
32262 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33233 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33236 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33319 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33322 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33599 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33602 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33679 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
33682 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
35570 { 3678 /* prfh */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
35573 { 3678 /* prfh */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
38053 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
38056 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
38139 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
38142 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendUXTW3216, AMFBS_HasSVE },
40747 case MCK_ZPRExtendUXTW3216: