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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10602 case MCK_ZPRExtendSXTW6464: {
12184 case MCK_ZPRExtendSXTW6464: return "MCK_ZPRExtendSXTW6464";
12795 { 88 /* adr */, AArch64::ADR_SXTW_ZZZ_D_3, Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64641_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK__91_, MCK_SVEVectorDReg, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
14973 { 1863 /* ld1d */, AArch64::GLD1D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
14981 { 1863 /* ld1d */, AArch64::GLD1D_SXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
15807 { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
15815 { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
16865 { 3673 /* prfd */, AArch64::PRFD_D_SXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
18308 { 5243 /* st1d */, AArch64::SST1D_SXTW_SCALED, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
18316 { 5243 /* st1d */, AArch64::SST1D_SXTW_SCALED, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
20153 { 88 /* adr */, AArch64::ADR_SXTW_ZZZ_D_3, Convert__SVEVectorDReg1_0__SVEVectorDReg1_2__ZPRExtendSXTW64641_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK__91_, MCK_SVEVectorDReg, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
22331 { 1863 /* ld1d */, AArch64::GLD1D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
22339 { 1863 /* ld1d */, AArch64::GLD1D_SXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
23165 { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_SCALED_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
23173 { 2457 /* ldff1d */, AArch64::GLDFF1D_SXTW_SCALED_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW64641_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
24223 { 3673 /* prfd */, AArch64::PRFD_D_SXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
25666 { 5243 /* st1d */, AArch64::SST1D_SXTW_SCALED, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
25674 { 5243 /* st1d */, AArch64::SST1D_SXTW_SCALED, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW64641_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW6464, MCK__93_ }, },
27790 { 88 /* adr */, 8 /* 3 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
27792 { 88 /* adr */, 8 /* 3 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
31245 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
31248 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
31291 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
31294 { 1863 /* ld1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
33089 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
33092 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
33135 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
33138 { 2457 /* ldff1d */, 64 /* 6 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
35514 { 3673 /* prfd */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
35517 { 3673 /* prfd */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
37901 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
37904 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
37947 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
37950 { 5243 /* st1d */, 16 /* 4 */, MCK_ZPRExtendSXTW6464, AMFBS_HasSVE },
40769 case MCK_ZPRExtendSXTW6464: