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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10458 case MCK_ZPRExtendSXTW3216: {
12168 case MCK_ZPRExtendSXTW3216: return "MCK_ZPRExtendSXTW3216";
15000 { 1868 /* ld1h */, AArch64::GLD1H_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15015 { 1868 /* ld1h */, AArch64::GLD1H_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15215 { 1957 /* ld1sh */, AArch64::GLD1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15229 { 1957 /* ld1sh */, AArch64::GLD1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15832 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15847 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15899 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
15913 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
16874 { 3678 /* prfh */, AArch64::PRFH_S_SXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
18335 { 5248 /* st1h */, AArch64::SST1H_S_SXTW_SCALED, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
18350 { 5248 /* st1h */, AArch64::SST1H_S_SXTW_SCALED, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
22358 { 1868 /* ld1h */, AArch64::GLD1H_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
22373 { 1868 /* ld1h */, AArch64::GLD1H_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
22573 { 1957 /* ld1sh */, AArch64::GLD1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
22587 { 1957 /* ld1sh */, AArch64::GLD1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
23190 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
23205 { 2464 /* ldff1h */, AArch64::GLDFF1H_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
23257 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
23271 { 2479 /* ldff1sh */, AArch64::GLDFF1SH_S_SXTW_SCALED_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__ZPRExtendSXTW32161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
24232 { 3678 /* prfh */, AArch64::PRFH_S_SXTW_SCALED, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
25693 { 5248 /* st1h */, AArch64::SST1H_S_SXTW_SCALED, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
25708 { 5248 /* st1h */, AArch64::SST1H_S_SXTW_SCALED, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_3__ZPRExtendSXTW32161_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_ZPRExtendSXTW3216, MCK__93_ }, },
31385 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
31388 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
31471 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
31474 { 1868 /* ld1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
32167 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
32170 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
32247 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
32250 { 1957 /* ld1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33221 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33224 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33307 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33310 { 2464 /* ldff1h */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33587 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33590 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33667 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
33670 { 2479 /* ldff1sh */, 64 /* 6 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
35564 { 3678 /* prfh */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
35567 { 3678 /* prfh */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
38041 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
38044 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
38127 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
38130 { 5248 /* st1h */, 16 /* 4 */, MCK_ZPRExtendSXTW3216, AMFBS_HasSVE },
40737 case MCK_ZPRExtendSXTW3216: