|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9932 case MCK_UImm6s4: {
12096 case MCK_UImm6s4: return "MCK_UImm6s4";
15160 { 1938 /* ld1rsw */, AArch64::LD1RSW_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
15161 { 1938 /* ld1rsw */, AArch64::LD1RSW_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
15166 { 1945 /* ld1rw */, AArch64::LD1RW_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
15167 { 1945 /* ld1rw */, AArch64::LD1RW_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
15168 { 1945 /* ld1rw */, AArch64::LD1RW_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
15169 { 1945 /* ld1rw */, AArch64::LD1RW_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22518 { 1938 /* ld1rsw */, AArch64::LD1RSW_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22519 { 1938 /* ld1rsw */, AArch64::LD1RSW_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22524 { 1945 /* ld1rw */, AArch64::LD1RW_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22525 { 1945 /* ld1rw */, AArch64::LD1RW_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22526 { 1945 /* ld1rw */, AArch64::LD1RW_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },
22527 { 1945 /* ld1rw */, AArch64::LD1RW_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__UImm6s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_UImm6s4, MCK__93_ }, },