reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
9887 case MCK_UImm5s8: { 12091 case MCK_UImm5s8: return "MCK_UImm5s8"; 14977 { 1863 /* ld1d */, AArch64::GLD1D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 14985 { 1863 /* ld1d */, AArch64::GLD1D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 15811 { 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 15819 { 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 16867 { 3673 /* prfd */, AArch64::PRFD_S_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s8, MCK__93_ }, }, 16868 { 3673 /* prfd */, AArch64::PRFD_D_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 18312 { 5243 /* st1d */, AArch64::SST1D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 18320 { 5243 /* st1d */, AArch64::SST1D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 22335 { 1863 /* ld1d */, AArch64::GLD1D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 22343 { 1863 /* ld1d */, AArch64::GLD1D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 23169 { 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 23177 { 2457 /* ldff1d */, AArch64::GLDFF1D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s81_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 24225 { 3673 /* prfd */, AArch64::PRFD_S_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s8, MCK__93_ }, }, 24226 { 3673 /* prfd */, AArch64::PRFD_D_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 25670 { 5243 /* st1d */, AArch64::SST1D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, }, 25678 { 5243 /* st1d */, AArch64::SST1D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s81_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s8, MCK__93_ }, },