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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9878 case MCK_UImm5s4: {
12090 case MCK_UImm5s4: return "MCK_UImm5s4";
15257 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15265 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15281 { 1969 /* ld1w */, AArch64::GLD1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
15289 { 1969 /* ld1w */, AArch64::GLD1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15295 { 1969 /* ld1w */, AArch64::GLD1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
15303 { 1969 /* ld1w */, AArch64::GLD1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15937 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15945 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15959 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
15967 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15973 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
15981 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
16899 { 3694 /* prfw */, AArch64::PRFW_S_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
16900 { 3694 /* prfw */, AArch64::PRFW_D_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
18382 { 5253 /* st1w */, AArch64::SST1W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
18390 { 5253 /* st1w */, AArch64::SST1W_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
18396 { 5253 /* st1w */, AArch64::SST1W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
18404 { 5253 /* st1w */, AArch64::SST1W_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22615 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22623 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22639 { 1969 /* ld1w */, AArch64::GLD1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
22647 { 1969 /* ld1w */, AArch64::GLD1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22653 { 1969 /* ld1w */, AArch64::GLD1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
22661 { 1969 /* ld1w */, AArch64::GLD1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23295 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23303 { 2487 /* ldff1sw */, AArch64::GLDFF1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23317 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
23325 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23331 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
23339 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
24257 { 3694 /* prfw */, AArch64::PRFW_S_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
24258 { 3694 /* prfw */, AArch64::PRFW_D_PZI, Convert__SVEPrefetch1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEPrefetch, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
25740 { 5253 /* st1w */, AArch64::SST1W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
25748 { 5253 /* st1w */, AArch64::SST1W_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
25754 { 5253 /* st1w */, AArch64::SST1W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
25762 { 5253 /* st1w */, AArch64::SST1W_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__UImm5s41_4, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },