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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10006 case MCK_TypedVectorList4_88: {
12106 case MCK_TypedVectorList4_88: return "MCK_TypedVectorList4_88";
14714 { 1854 /* ld1 */, AArch64::LD1Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14784 { 1854 /* ld1 */, AArch64::LD1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14785 { 1854 /* ld1 */, AArch64::LD1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15565 { 2032 /* ld4 */, AArch64::LD4Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15584 { 2032 /* ld4 */, AArch64::LD4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15585 { 2032 /* ld4 */, AArch64::LD4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15641 { 2051 /* ld4r */, AArch64::LD4Rv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15663 { 2051 /* ld4r */, AArch64::LD4Rv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
15664 { 2051 /* ld4r */, AArch64::LD4Rv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18049 { 5234 /* st1 */, AArch64::ST1Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18119 { 5234 /* st1 */, AArch64::ST1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18120 { 5234 /* st1 */, AArch64::ST1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18574 { 5311 /* st4 */, AArch64::ST4Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18593 { 5311 /* st4 */, AArch64::ST4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18594 { 5311 /* st4 */, AArch64::ST4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22072 { 1854 /* ld1 */, AArch64::LD1Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22142 { 1854 /* ld1 */, AArch64::LD1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22143 { 1854 /* ld1 */, AArch64::LD1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22923 { 2032 /* ld4 */, AArch64::LD4Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22942 { 2032 /* ld4 */, AArch64::LD4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22943 { 2032 /* ld4 */, AArch64::LD4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22999 { 2051 /* ld4r */, AArch64::LD4Rv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23021 { 2051 /* ld4r */, AArch64::LD4Rv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
23022 { 2051 /* ld4r */, AArch64::LD4Rv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25407 { 5234 /* st1 */, AArch64::ST1Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25477 { 5234 /* st1 */, AArch64::ST1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25478 { 5234 /* st1 */, AArch64::ST1Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25932 { 5311 /* st4 */, AArch64::ST4Fourv8b, Convert__TypedVectorList4_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25951 { 5311 /* st4 */, AArch64::ST4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25952 { 5311 /* st4 */, AArch64::ST4Fourv8b_POST, Convert__Reg1_2__TypedVectorList4_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },