|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10013 case MCK_TypedVectorList4_816: {
12107 case MCK_TypedVectorList4_816: return "MCK_TypedVectorList4_816";
14715 { 1854 /* ld1 */, AArch64::LD1Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14786 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14787 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15566 { 2032 /* ld4 */, AArch64::LD4Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15586 { 2032 /* ld4 */, AArch64::LD4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
15587 { 2032 /* ld4 */, AArch64::LD4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15642 { 2051 /* ld4r */, AArch64::LD4Rv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15665 { 2051 /* ld4r */, AArch64::LD4Rv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15666 { 2051 /* ld4r */, AArch64::LD4Rv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18050 { 5234 /* st1 */, AArch64::ST1Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18121 { 5234 /* st1 */, AArch64::ST1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18122 { 5234 /* st1 */, AArch64::ST1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18575 { 5311 /* st4 */, AArch64::ST4Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18595 { 5311 /* st4 */, AArch64::ST4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18596 { 5311 /* st4 */, AArch64::ST4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22073 { 1854 /* ld1 */, AArch64::LD1Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22144 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22145 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22924 { 2032 /* ld4 */, AArch64::LD4Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22944 { 2032 /* ld4 */, AArch64::LD4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22945 { 2032 /* ld4 */, AArch64::LD4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
23000 { 2051 /* ld4r */, AArch64::LD4Rv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23023 { 2051 /* ld4r */, AArch64::LD4Rv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
23024 { 2051 /* ld4r */, AArch64::LD4Rv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25408 { 5234 /* st1 */, AArch64::ST1Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25479 { 5234 /* st1 */, AArch64::ST1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25480 { 5234 /* st1 */, AArch64::ST1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25933 { 5311 /* st4 */, AArch64::ST4Fourv8h, Convert__TypedVectorList4_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25953 { 5311 /* st4 */, AArch64::ST4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25954 { 5311 /* st4 */, AArch64::ST4Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },