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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9992 case MCK_TypedVectorList4_432: {
12104 case MCK_TypedVectorList4_432: return "MCK_TypedVectorList4_432";
14713 { 1854 /* ld1 */, AArch64::LD1Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14782 { 1854 /* ld1 */, AArch64::LD1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14783 { 1854 /* ld1 */, AArch64::LD1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15564 { 2032 /* ld4 */, AArch64::LD4Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15582 { 2032 /* ld4 */, AArch64::LD4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
15583 { 2032 /* ld4 */, AArch64::LD4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15640 { 2051 /* ld4r */, AArch64::LD4Rv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15661 { 2051 /* ld4r */, AArch64::LD4Rv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
15662 { 2051 /* ld4r */, AArch64::LD4Rv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18048 { 5234 /* st1 */, AArch64::ST1Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18117 { 5234 /* st1 */, AArch64::ST1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18118 { 5234 /* st1 */, AArch64::ST1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18573 { 5311 /* st4 */, AArch64::ST4Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18591 { 5311 /* st4 */, AArch64::ST4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18592 { 5311 /* st4 */, AArch64::ST4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22071 { 1854 /* ld1 */, AArch64::LD1Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22140 { 1854 /* ld1 */, AArch64::LD1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22141 { 1854 /* ld1 */, AArch64::LD1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22922 { 2032 /* ld4 */, AArch64::LD4Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22940 { 2032 /* ld4 */, AArch64::LD4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22941 { 2032 /* ld4 */, AArch64::LD4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22998 { 2051 /* ld4r */, AArch64::LD4Rv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23019 { 2051 /* ld4r */, AArch64::LD4Rv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
23020 { 2051 /* ld4r */, AArch64::LD4Rv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25406 { 5234 /* st1 */, AArch64::ST1Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25475 { 5234 /* st1 */, AArch64::ST1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25476 { 5234 /* st1 */, AArch64::ST1Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25931 { 5311 /* st4 */, AArch64::ST4Fourv4s, Convert__TypedVectorList4_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25949 { 5311 /* st4 */, AArch64::ST4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25950 { 5311 /* st4 */, AArch64::ST4Fourv4s_POST, Convert__Reg1_2__TypedVectorList4_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },