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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9985 case MCK_TypedVectorList4_416: {
12103 case MCK_TypedVectorList4_416: return "MCK_TypedVectorList4_416";
14712 { 1854 /* ld1 */, AArch64::LD1Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14780 { 1854 /* ld1 */, AArch64::LD1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14781 { 1854 /* ld1 */, AArch64::LD1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15563 { 2032 /* ld4 */, AArch64::LD4Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15580 { 2032 /* ld4 */, AArch64::LD4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15581 { 2032 /* ld4 */, AArch64::LD4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15639 { 2051 /* ld4r */, AArch64::LD4Rv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15659 { 2051 /* ld4r */, AArch64::LD4Rv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15660 { 2051 /* ld4r */, AArch64::LD4Rv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18047 { 5234 /* st1 */, AArch64::ST1Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18115 { 5234 /* st1 */, AArch64::ST1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18116 { 5234 /* st1 */, AArch64::ST1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18572 { 5311 /* st4 */, AArch64::ST4Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18589 { 5311 /* st4 */, AArch64::ST4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18590 { 5311 /* st4 */, AArch64::ST4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22070 { 1854 /* ld1 */, AArch64::LD1Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22138 { 1854 /* ld1 */, AArch64::LD1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22139 { 1854 /* ld1 */, AArch64::LD1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22921 { 2032 /* ld4 */, AArch64::LD4Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22938 { 2032 /* ld4 */, AArch64::LD4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22939 { 2032 /* ld4 */, AArch64::LD4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22997 { 2051 /* ld4r */, AArch64::LD4Rv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23017 { 2051 /* ld4r */, AArch64::LD4Rv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
23018 { 2051 /* ld4r */, AArch64::LD4Rv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25405 { 5234 /* st1 */, AArch64::ST1Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25473 { 5234 /* st1 */, AArch64::ST1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25474 { 5234 /* st1 */, AArch64::ST1Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25930 { 5311 /* st4 */, AArch64::ST4Fourv4h, Convert__TypedVectorList4_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25947 { 5311 /* st4 */, AArch64::ST4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25948 { 5311 /* st4 */, AArch64::ST4Fourv4h_POST, Convert__Reg1_2__TypedVectorList4_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },