|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9971 case MCK_TypedVectorList4_264: {
12101 case MCK_TypedVectorList4_264: return "MCK_TypedVectorList4_264";
14710 { 1854 /* ld1 */, AArch64::LD1Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14776 { 1854 /* ld1 */, AArch64::LD1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14777 { 1854 /* ld1 */, AArch64::LD1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15561 { 2032 /* ld4 */, AArch64::LD4Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15576 { 2032 /* ld4 */, AArch64::LD4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
15577 { 2032 /* ld4 */, AArch64::LD4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15637 { 2051 /* ld4r */, AArch64::LD4Rv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15655 { 2051 /* ld4r */, AArch64::LD4Rv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15656 { 2051 /* ld4r */, AArch64::LD4Rv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18045 { 5234 /* st1 */, AArch64::ST1Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18111 { 5234 /* st1 */, AArch64::ST1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18112 { 5234 /* st1 */, AArch64::ST1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18570 { 5311 /* st4 */, AArch64::ST4Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18585 { 5311 /* st4 */, AArch64::ST4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18586 { 5311 /* st4 */, AArch64::ST4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22068 { 1854 /* ld1 */, AArch64::LD1Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22134 { 1854 /* ld1 */, AArch64::LD1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22135 { 1854 /* ld1 */, AArch64::LD1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22919 { 2032 /* ld4 */, AArch64::LD4Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22934 { 2032 /* ld4 */, AArch64::LD4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22935 { 2032 /* ld4 */, AArch64::LD4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22995 { 2051 /* ld4r */, AArch64::LD4Rv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23013 { 2051 /* ld4r */, AArch64::LD4Rv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
23014 { 2051 /* ld4r */, AArch64::LD4Rv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25403 { 5234 /* st1 */, AArch64::ST1Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25469 { 5234 /* st1 */, AArch64::ST1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25470 { 5234 /* st1 */, AArch64::ST1Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25928 { 5311 /* st4 */, AArch64::ST4Fourv2d, Convert__TypedVectorList4_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25943 { 5311 /* st4 */, AArch64::ST4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25944 { 5311 /* st4 */, AArch64::ST4Fourv2d_POST, Convert__Reg1_2__TypedVectorList4_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },