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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9978 case MCK_TypedVectorList4_232: {
12102 case MCK_TypedVectorList4_232: return "MCK_TypedVectorList4_232";
14711 { 1854 /* ld1 */, AArch64::LD1Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14778 { 1854 /* ld1 */, AArch64::LD1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14779 { 1854 /* ld1 */, AArch64::LD1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15562 { 2032 /* ld4 */, AArch64::LD4Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15578 { 2032 /* ld4 */, AArch64::LD4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15579 { 2032 /* ld4 */, AArch64::LD4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15638 { 2051 /* ld4r */, AArch64::LD4Rv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15657 { 2051 /* ld4r */, AArch64::LD4Rv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
15658 { 2051 /* ld4r */, AArch64::LD4Rv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18046 { 5234 /* st1 */, AArch64::ST1Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18113 { 5234 /* st1 */, AArch64::ST1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18114 { 5234 /* st1 */, AArch64::ST1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18571 { 5311 /* st4 */, AArch64::ST4Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18587 { 5311 /* st4 */, AArch64::ST4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18588 { 5311 /* st4 */, AArch64::ST4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22069 { 1854 /* ld1 */, AArch64::LD1Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22136 { 1854 /* ld1 */, AArch64::LD1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22137 { 1854 /* ld1 */, AArch64::LD1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22920 { 2032 /* ld4 */, AArch64::LD4Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22936 { 2032 /* ld4 */, AArch64::LD4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22937 { 2032 /* ld4 */, AArch64::LD4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22996 { 2051 /* ld4r */, AArch64::LD4Rv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23015 { 2051 /* ld4r */, AArch64::LD4Rv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
23016 { 2051 /* ld4r */, AArch64::LD4Rv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25404 { 5234 /* st1 */, AArch64::ST1Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25471 { 5234 /* st1 */, AArch64::ST1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25472 { 5234 /* st1 */, AArch64::ST1Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25929 { 5311 /* st4 */, AArch64::ST4Fourv2s, Convert__TypedVectorList4_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25945 { 5311 /* st4 */, AArch64::ST4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25946 { 5311 /* st4 */, AArch64::ST4Fourv2s_POST, Convert__Reg1_2__TypedVectorList4_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },