|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9957 case MCK_TypedVectorList4_168: {
12099 case MCK_TypedVectorList4_168: return "MCK_TypedVectorList4_168";
14708 { 1854 /* ld1 */, AArch64::LD1Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14772 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14773 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15560 { 2032 /* ld4 */, AArch64::LD4Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15574 { 2032 /* ld4 */, AArch64::LD4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
15575 { 2032 /* ld4 */, AArch64::LD4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15635 { 2051 /* ld4r */, AArch64::LD4Rv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15651 { 2051 /* ld4r */, AArch64::LD4Rv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
15652 { 2051 /* ld4r */, AArch64::LD4Rv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18043 { 5234 /* st1 */, AArch64::ST1Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18107 { 5234 /* st1 */, AArch64::ST1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18108 { 5234 /* st1 */, AArch64::ST1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18569 { 5311 /* st4 */, AArch64::ST4Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18583 { 5311 /* st4 */, AArch64::ST4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
18584 { 5311 /* st4 */, AArch64::ST4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
19096 { 6111 /* tbl */, AArch64::TBLv16i8Four, Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList4_168, MCK_VectorReg128, MCK__DOT_16b }, },
19100 { 6111 /* tbl */, AArch64::TBLv8i8Four, Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList4_168, MCK_VectorReg64, MCK__DOT_8b }, },
19119 { 6120 /* tbx */, AArch64::TBXv16i8Four, Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList4_168, MCK_VectorReg128, MCK__DOT_16b }, },
19123 { 6120 /* tbx */, AArch64::TBXv8i8Four, Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList4_168, MCK_VectorReg64, MCK__DOT_8b }, },
22066 { 1854 /* ld1 */, AArch64::LD1Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22130 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22131 { 1854 /* ld1 */, AArch64::LD1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22918 { 2032 /* ld4 */, AArch64::LD4Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22932 { 2032 /* ld4 */, AArch64::LD4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22933 { 2032 /* ld4 */, AArch64::LD4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22993 { 2051 /* ld4r */, AArch64::LD4Rv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23009 { 2051 /* ld4r */, AArch64::LD4Rv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
23010 { 2051 /* ld4r */, AArch64::LD4Rv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25401 { 5234 /* st1 */, AArch64::ST1Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25465 { 5234 /* st1 */, AArch64::ST1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25466 { 5234 /* st1 */, AArch64::ST1Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25927 { 5311 /* st4 */, AArch64::ST4Fourv16b, Convert__TypedVectorList4_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25941 { 5311 /* st4 */, AArch64::ST4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
25942 { 5311 /* st4 */, AArch64::ST4Fourv16b_POST, Convert__Reg1_2__TypedVectorList4_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
26454 { 6111 /* tbl */, AArch64::TBLv16i8Four, Convert__VectorReg1281_0__TypedVectorList4_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList4_168, MCK_VectorReg128, MCK__DOT_16b }, },
26458 { 6111 /* tbl */, AArch64::TBLv8i8Four, Convert__VectorReg641_0__TypedVectorList4_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList4_168, MCK_VectorReg64, MCK__DOT_8b }, },
26477 { 6120 /* tbx */, AArch64::TBXv16i8Four, Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList4_168, MCK_VectorReg128, MCK__DOT_16b }, },
26481 { 6120 /* tbx */, AArch64::TBXv8i8Four, Convert__VectorReg641_0__Tie0_1_1__TypedVectorList4_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList4_168, MCK_VectorReg64, MCK__DOT_8b }, },