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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9964 case MCK_TypedVectorList4_164: {
12100 case MCK_TypedVectorList4_164: return "MCK_TypedVectorList4_164";
14709 { 1854 /* ld1 */, AArch64::LD1Fourv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14774 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14775 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15636 { 2051 /* ld4r */, AArch64::LD4Rv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15653 { 2051 /* ld4r */, AArch64::LD4Rv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
15654 { 2051 /* ld4r */, AArch64::LD4Rv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18044 { 5234 /* st1 */, AArch64::ST1Fourv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18109 { 5234 /* st1 */, AArch64::ST1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
18110 { 5234 /* st1 */, AArch64::ST1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22067 { 1854 /* ld1 */, AArch64::LD1Fourv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22132 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22133 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22994 { 2051 /* ld4r */, AArch64::LD4Rv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23011 { 2051 /* ld4r */, AArch64::LD4Rv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
23012 { 2051 /* ld4r */, AArch64::LD4Rv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25402 { 5234 /* st1 */, AArch64::ST1Fourv1d, Convert__TypedVectorList4_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25467 { 5234 /* st1 */, AArch64::ST1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
25468 { 5234 /* st1 */, AArch64::ST1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },