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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10160 case MCK_TypedVectorList3_164: {
12128 case MCK_TypedVectorList3_164: return "MCK_TypedVectorList3_164";
14725 { 1854 /* ld1 */, AArch64::LD1Threev1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14810 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
14811 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15510 { 2022 /* ld3r */, AArch64::LD3Rv1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15527 { 2022 /* ld3r */, AArch64::LD3Rv1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
15528 { 2022 /* ld3r */, AArch64::LD3Rv1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18060 { 5234 /* st1 */, AArch64::ST1Threev1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18145 { 5234 /* st1 */, AArch64::ST1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
18146 { 5234 /* st1 */, AArch64::ST1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22083 { 1854 /* ld1 */, AArch64::LD1Threev1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22168 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22169 { 1854 /* ld1 */, AArch64::LD1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22868 { 2022 /* ld3r */, AArch64::LD3Rv1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22885 { 2022 /* ld3r */, AArch64::LD3Rv1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
22886 { 2022 /* ld3r */, AArch64::LD3Rv1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25418 { 5234 /* st1 */, AArch64::ST1Threev1d, Convert__TypedVectorList3_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25503 { 5234 /* st1 */, AArch64::ST1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_24 }, },
25504 { 5234 /* st1 */, AArch64::ST1Threev1d_POST, Convert__Reg1_2__TypedVectorList3_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },