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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10258 case MCK_TypedVectorList2_164: {
12142 case MCK_TypedVectorList2_164: return "MCK_TypedVectorList2_164";
14733 { 1854 /* ld1 */, AArch64::LD1Twov1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14826 { 1854 /* ld1 */, AArch64::LD1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
14827 { 1854 /* ld1 */, AArch64::LD1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15384 { 1993 /* ld2r */, AArch64::LD2Rv1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15401 { 1993 /* ld2r */, AArch64::LD2Rv1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
15402 { 1993 /* ld2r */, AArch64::LD2Rv1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18068 { 5234 /* st1 */, AArch64::ST1Twov1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18161 { 5234 /* st1 */, AArch64::ST1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
18162 { 5234 /* st1 */, AArch64::ST1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22091 { 1854 /* ld1 */, AArch64::LD1Twov1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22184 { 1854 /* ld1 */, AArch64::LD1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22185 { 1854 /* ld1 */, AArch64::LD1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22742 { 1993 /* ld2r */, AArch64::LD2Rv1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22759 { 1993 /* ld2r */, AArch64::LD2Rv1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22760 { 1993 /* ld2r */, AArch64::LD2Rv1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25426 { 5234 /* st1 */, AArch64::ST1Twov1d, Convert__TypedVectorList2_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25519 { 5234 /* st1 */, AArch64::ST1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
25520 { 5234 /* st1 */, AArch64::ST1Twov1d_POST, Convert__Reg1_2__TypedVectorList2_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },