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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10104 case MCK_TypedVectorList1_88: {
12120 case MCK_TypedVectorList1_88: return "MCK_TypedVectorList1_88";
14722 { 1854 /* ld1 */, AArch64::LD1Onev8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14800 { 1854 /* ld1 */, AArch64::LD1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14801 { 1854 /* ld1 */, AArch64::LD1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15040 { 1873 /* ld1r */, AArch64::LD1Rv8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15062 { 1873 /* ld1r */, AArch64::LD1Rv8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_1 }, },
15063 { 1873 /* ld1r */, AArch64::LD1Rv8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18057 { 5234 /* st1 */, AArch64::ST1Onev8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18135 { 5234 /* st1 */, AArch64::ST1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
18136 { 5234 /* st1 */, AArch64::ST1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22080 { 1854 /* ld1 */, AArch64::LD1Onev8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22158 { 1854 /* ld1 */, AArch64::LD1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22159 { 1854 /* ld1 */, AArch64::LD1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22398 { 1873 /* ld1r */, AArch64::LD1Rv8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22420 { 1873 /* ld1r */, AArch64::LD1Rv8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_1 }, },
22421 { 1873 /* ld1r */, AArch64::LD1Rv8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25415 { 5234 /* st1 */, AArch64::ST1Onev8b, Convert__TypedVectorList1_881_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25493 { 5234 /* st1 */, AArch64::ST1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
25494 { 5234 /* st1 */, AArch64::ST1Onev8b_POST, Convert__Reg1_2__TypedVectorList1_881_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_88, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },