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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10111 case MCK_TypedVectorList1_816: {
12121 case MCK_TypedVectorList1_816: return "MCK_TypedVectorList1_816";
14723 { 1854 /* ld1 */, AArch64::LD1Onev8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14802 { 1854 /* ld1 */, AArch64::LD1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
14803 { 1854 /* ld1 */, AArch64::LD1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15041 { 1873 /* ld1r */, AArch64::LD1Rv8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15064 { 1873 /* ld1r */, AArch64::LD1Rv8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_2 }, },
15065 { 1873 /* ld1r */, AArch64::LD1Rv8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18058 { 5234 /* st1 */, AArch64::ST1Onev8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18137 { 5234 /* st1 */, AArch64::ST1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
18138 { 5234 /* st1 */, AArch64::ST1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22081 { 1854 /* ld1 */, AArch64::LD1Onev8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22160 { 1854 /* ld1 */, AArch64::LD1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22161 { 1854 /* ld1 */, AArch64::LD1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22399 { 1873 /* ld1r */, AArch64::LD1Rv8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22422 { 1873 /* ld1r */, AArch64::LD1Rv8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_2 }, },
22423 { 1873 /* ld1r */, AArch64::LD1Rv8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25416 { 5234 /* st1 */, AArch64::ST1Onev8h, Convert__TypedVectorList1_8161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25495 { 5234 /* st1 */, AArch64::ST1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
25496 { 5234 /* st1 */, AArch64::ST1Onev8h_POST, Convert__Reg1_2__TypedVectorList1_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },