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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10090 case MCK_TypedVectorList1_432: {
12118 case MCK_TypedVectorList1_432: return "MCK_TypedVectorList1_432";
14721 { 1854 /* ld1 */, AArch64::LD1Onev4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14798 { 1854 /* ld1 */, AArch64::LD1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
14799 { 1854 /* ld1 */, AArch64::LD1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15039 { 1873 /* ld1r */, AArch64::LD1Rv4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15060 { 1873 /* ld1r */, AArch64::LD1Rv4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
15061 { 1873 /* ld1r */, AArch64::LD1Rv4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18056 { 5234 /* st1 */, AArch64::ST1Onev4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18133 { 5234 /* st1 */, AArch64::ST1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
18134 { 5234 /* st1 */, AArch64::ST1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22079 { 1854 /* ld1 */, AArch64::LD1Onev4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22156 { 1854 /* ld1 */, AArch64::LD1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22157 { 1854 /* ld1 */, AArch64::LD1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22397 { 1873 /* ld1r */, AArch64::LD1Rv4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22418 { 1873 /* ld1r */, AArch64::LD1Rv4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
22419 { 1873 /* ld1r */, AArch64::LD1Rv4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25414 { 5234 /* st1 */, AArch64::ST1Onev4s, Convert__TypedVectorList1_4321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25491 { 5234 /* st1 */, AArch64::ST1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
25492 { 5234 /* st1 */, AArch64::ST1Onev4s_POST, Convert__Reg1_2__TypedVectorList1_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },