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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10083 case MCK_TypedVectorList1_416: {
12117 case MCK_TypedVectorList1_416: return "MCK_TypedVectorList1_416";
14720 { 1854 /* ld1 */, AArch64::LD1Onev4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14796 { 1854 /* ld1 */, AArch64::LD1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14797 { 1854 /* ld1 */, AArch64::LD1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15038 { 1873 /* ld1r */, AArch64::LD1Rv4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15058 { 1873 /* ld1r */, AArch64::LD1Rv4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_2 }, },
15059 { 1873 /* ld1r */, AArch64::LD1Rv4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18055 { 5234 /* st1 */, AArch64::ST1Onev4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18131 { 5234 /* st1 */, AArch64::ST1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
18132 { 5234 /* st1 */, AArch64::ST1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22078 { 1854 /* ld1 */, AArch64::LD1Onev4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22154 { 1854 /* ld1 */, AArch64::LD1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22155 { 1854 /* ld1 */, AArch64::LD1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22396 { 1873 /* ld1r */, AArch64::LD1Rv4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22416 { 1873 /* ld1r */, AArch64::LD1Rv4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_2 }, },
22417 { 1873 /* ld1r */, AArch64::LD1Rv4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25413 { 5234 /* st1 */, AArch64::ST1Onev4h, Convert__TypedVectorList1_4161_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25489 { 5234 /* st1 */, AArch64::ST1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
25490 { 5234 /* st1 */, AArch64::ST1Onev4h_POST, Convert__Reg1_2__TypedVectorList1_4161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_416, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },