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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10069 case MCK_TypedVectorList1_264: {
12115 case MCK_TypedVectorList1_264: return "MCK_TypedVectorList1_264";
14718 { 1854 /* ld1 */, AArch64::LD1Onev2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14792 { 1854 /* ld1 */, AArch64::LD1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
14793 { 1854 /* ld1 */, AArch64::LD1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15036 { 1873 /* ld1r */, AArch64::LD1Rv2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15054 { 1873 /* ld1r */, AArch64::LD1Rv2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15055 { 1873 /* ld1r */, AArch64::LD1Rv2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18053 { 5234 /* st1 */, AArch64::ST1Onev2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18127 { 5234 /* st1 */, AArch64::ST1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
18128 { 5234 /* st1 */, AArch64::ST1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22076 { 1854 /* ld1 */, AArch64::LD1Onev2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22150 { 1854 /* ld1 */, AArch64::LD1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22151 { 1854 /* ld1 */, AArch64::LD1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22394 { 1873 /* ld1r */, AArch64::LD1Rv2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22412 { 1873 /* ld1r */, AArch64::LD1Rv2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22413 { 1873 /* ld1r */, AArch64::LD1Rv2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25411 { 5234 /* st1 */, AArch64::ST1Onev2d, Convert__TypedVectorList1_2641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25485 { 5234 /* st1 */, AArch64::ST1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
25486 { 5234 /* st1 */, AArch64::ST1Onev2d_POST, Convert__Reg1_2__TypedVectorList1_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },