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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10076 case MCK_TypedVectorList1_232: {
12116 case MCK_TypedVectorList1_232: return "MCK_TypedVectorList1_232";
14719 { 1854 /* ld1 */, AArch64::LD1Onev2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14794 { 1854 /* ld1 */, AArch64::LD1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14795 { 1854 /* ld1 */, AArch64::LD1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15037 { 1873 /* ld1r */, AArch64::LD1Rv2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15056 { 1873 /* ld1r */, AArch64::LD1Rv2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
15057 { 1873 /* ld1r */, AArch64::LD1Rv2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18054 { 5234 /* st1 */, AArch64::ST1Onev2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18129 { 5234 /* st1 */, AArch64::ST1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
18130 { 5234 /* st1 */, AArch64::ST1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22077 { 1854 /* ld1 */, AArch64::LD1Onev2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22152 { 1854 /* ld1 */, AArch64::LD1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22153 { 1854 /* ld1 */, AArch64::LD1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22395 { 1873 /* ld1r */, AArch64::LD1Rv2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22414 { 1873 /* ld1r */, AArch64::LD1Rv2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_4 }, },
22415 { 1873 /* ld1r */, AArch64::LD1Rv2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25412 { 5234 /* st1 */, AArch64::ST1Onev2s, Convert__TypedVectorList1_2321_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25487 { 5234 /* st1 */, AArch64::ST1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
25488 { 5234 /* st1 */, AArch64::ST1Onev2s_POST, Convert__Reg1_2__TypedVectorList1_2321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_232, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },