|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10055 case MCK_TypedVectorList1_168: {
12113 case MCK_TypedVectorList1_168: return "MCK_TypedVectorList1_168";
14716 { 1854 /* ld1 */, AArch64::LD1Onev16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14788 { 1854 /* ld1 */, AArch64::LD1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
14789 { 1854 /* ld1 */, AArch64::LD1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15034 { 1873 /* ld1r */, AArch64::LD1Rv16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15050 { 1873 /* ld1r */, AArch64::LD1Rv16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_1 }, },
15051 { 1873 /* ld1r */, AArch64::LD1Rv16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18051 { 5234 /* st1 */, AArch64::ST1Onev16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18123 { 5234 /* st1 */, AArch64::ST1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
18124 { 5234 /* st1 */, AArch64::ST1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
19097 { 6111 /* tbl */, AArch64::TBLv16i8One, Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList1_168, MCK_VectorReg128, MCK__DOT_16b }, },
19101 { 6111 /* tbl */, AArch64::TBLv8i8One, Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList1_168, MCK_VectorReg64, MCK__DOT_8b }, },
19120 { 6120 /* tbx */, AArch64::TBXv16i8One, Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList1_168, MCK_VectorReg128, MCK__DOT_16b }, },
19124 { 6120 /* tbx */, AArch64::TBXv8i8One, Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList1_168, MCK_VectorReg64, MCK__DOT_8b }, },
22074 { 1854 /* ld1 */, AArch64::LD1Onev16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22146 { 1854 /* ld1 */, AArch64::LD1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
22147 { 1854 /* ld1 */, AArch64::LD1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22392 { 1873 /* ld1r */, AArch64::LD1Rv16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22408 { 1873 /* ld1r */, AArch64::LD1Rv16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_1 }, },
22409 { 1873 /* ld1r */, AArch64::LD1Rv16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25409 { 5234 /* st1 */, AArch64::ST1Onev16b, Convert__TypedVectorList1_1681_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25481 { 5234 /* st1 */, AArch64::ST1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_16 }, },
25482 { 5234 /* st1 */, AArch64::ST1Onev16b_POST, Convert__Reg1_2__TypedVectorList1_1681_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_168, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
26455 { 6111 /* tbl */, AArch64::TBLv16i8One, Convert__VectorReg1281_0__TypedVectorList1_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList1_168, MCK_VectorReg128, MCK__DOT_16b }, },
26459 { 6111 /* tbl */, AArch64::TBLv8i8One, Convert__VectorReg641_0__TypedVectorList1_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList1_168, MCK_VectorReg64, MCK__DOT_8b }, },
26478 { 6120 /* tbx */, AArch64::TBXv16i8One, Convert__VectorReg1281_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg1281_3, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_TypedVectorList1_168, MCK_VectorReg128, MCK__DOT_16b }, },
26482 { 6120 /* tbx */, AArch64::TBXv8i8One, Convert__VectorReg641_0__Tie0_1_1__TypedVectorList1_1681_2__VectorReg641_3, AMFBS_HasNEON, { MCK_VectorReg64, MCK__DOT_8b, MCK_TypedVectorList1_168, MCK_VectorReg64, MCK__DOT_8b }, },