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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10062 case MCK_TypedVectorList1_164: {
12114 case MCK_TypedVectorList1_164: return "MCK_TypedVectorList1_164";
14717 { 1854 /* ld1 */, AArch64::LD1Onev1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
14790 { 1854 /* ld1 */, AArch64::LD1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14791 { 1854 /* ld1 */, AArch64::LD1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15035 { 1873 /* ld1r */, AArch64::LD1Rv1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15052 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15053 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
18052 { 5234 /* st1 */, AArch64::ST1Onev1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18125 { 5234 /* st1 */, AArch64::ST1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
18126 { 5234 /* st1 */, AArch64::ST1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22075 { 1854 /* ld1 */, AArch64::LD1Onev1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22148 { 1854 /* ld1 */, AArch64::LD1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22149 { 1854 /* ld1 */, AArch64::LD1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22393 { 1873 /* ld1r */, AArch64::LD1Rv1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22410 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22411 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
25410 { 5234 /* st1 */, AArch64::ST1Onev1d, Convert__TypedVectorList1_1641_0__Reg1_2, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25483 { 5234 /* st1 */, AArch64::ST1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
25484 { 5234 /* st1 */, AArch64::ST1Onev1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },