reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10674 case MCK_SVEVectorQReg: { 12192 case MCK_SVEVectorQReg: return "MCK_SVEVectorQReg"; 13473 { 962 /* dup */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 13473 { 962 /* dup */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 16538 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__FPR128asZPR1_1__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_FPR128asZPR }, }, 16555 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 16555 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 16836 { 3648 /* pmullb */, AArch64::PMULLB_ZZZ_Q, Convert__SVEVectorQReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2AES, { MCK_SVEVectorQReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 16839 { 3655 /* pmullt */, AArch64::PMULLT_ZZZ_Q, Convert__SVEVectorQReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2AES, { MCK_SVEVectorQReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 20835 { 962 /* dup */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 20835 { 962 /* dup */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 23896 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__FPR128asZPR1_1__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_FPR128asZPR }, }, 23925 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 23925 { 3356 /* mov */, AArch64::DUP_ZZI_Q, Convert__SVEVectorQReg1_0__SVEVectorQReg1_1__SVEIndexRange0_31_2, AMFBS_HasSVE, { MCK_SVEVectorQReg, MCK_SVEVectorQReg, MCK_SVEIndexRange0_3 }, }, 24194 { 3648 /* pmullb */, AArch64::PMULLB_ZZZ_Q, Convert__SVEVectorQReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2AES, { MCK_SVEVectorQReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 24197 { 3655 /* pmullt */, AArch64::PMULLT_ZZZ_Q, Convert__SVEVectorQReg1_0__SVEVectorDReg1_1__SVEVectorDReg1_2, AMFBS_HasSVE2AES, { MCK_SVEVectorQReg, MCK_SVEVectorDReg, MCK_SVEVectorDReg }, }, 29292 { 962 /* dup */, 3 /* 0, 1 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 29293 { 962 /* dup */, 3 /* 0, 1 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 34950 { 3356 /* mov */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 34951 { 3356 /* mov */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 34992 { 3356 /* mov */, 3 /* 0, 1 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 34993 { 3356 /* mov */, 3 /* 0, 1 */, MCK_SVEVectorQReg, AMFBS_HasSVE }, 35364 { 3648 /* pmullb */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE2AES }, 35366 { 3648 /* pmullb */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE2AES }, 35376 { 3655 /* pmullt */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE2AES }, 35378 { 3655 /* pmullt */, 1 /* 0 */, MCK_SVEVectorQReg, AMFBS_HasSVE2AES }, 40785 case MCK_SVEVectorQReg: