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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10922 case MCK_SVEVectorList332: {
12224 case MCK_SVEVectorList332: return "MCK_SVEVectorList332";
15557 { 2027 /* ld3w */, AArch64::LD3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15558 { 2027 /* ld3w */, AArch64::LD3W, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
15559 { 2027 /* ld3w */, AArch64::LD3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s3, MCK_mul, MCK_vl, MCK__93_ }, },
18566 { 5306 /* st3w */, AArch64::ST3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18567 { 5306 /* st3w */, AArch64::ST3W, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
18568 { 5306 /* st3w */, AArch64::ST3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s3, MCK_mul, MCK_vl, MCK__93_ }, },
22915 { 2027 /* ld3w */, AArch64::LD3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22916 { 2027 /* ld3w */, AArch64::LD3W, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
22917 { 2027 /* ld3w */, AArch64::LD3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s31_6, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s3, MCK_mul, MCK_vl, MCK__93_ }, },
25924 { 5306 /* st3w */, AArch64::ST3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25925 { 5306 /* st3w */, AArch64::ST3W, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted321_4, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted32, MCK__93_ }, },
25926 { 5306 /* st3w */, AArch64::ST3W_IMM, Convert__SVEVectorList3321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s31_4, AMFBS_HasSVE, { MCK_SVEVectorList332, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s3, MCK_mul, MCK_vl, MCK__93_ }, },
32775 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
32777 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
32780 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
32783 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
32785 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
32787 { 2027 /* ld3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38543 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38545 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38548 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38551 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38553 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
38555 { 5306 /* st3w */, 1 /* 0 */, MCK_SVEVectorList332, AMFBS_HasSVE },
40829 case MCK_SVEVectorList332: