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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10880 case MCK_SVEVectorList28: {
12218 case MCK_SVEVectorList28: return "MCK_SVEVectorList28";
13546 { 1029 /* ext */, AArch64::EXT_ZZI_B, Convert__SVEVectorBReg1_0__SVEVectorList281_1__Imm0_2551_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorList28, MCK_Imm0_255 }, },
15374 { 1978 /* ld2b */, AArch64::LD2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15375 { 1978 /* ld2b */, AArch64::LD2B, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted8, MCK__93_ }, },
15376 { 1978 /* ld2b */, AArch64::LD2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
17415 { 4563 /* splice */, AArch64::SPLICE_ZPZZ_B, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorList281_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorList28 }, },
18475 { 5262 /* st2b */, AArch64::ST2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18476 { 5262 /* st2b */, AArch64::ST2B, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted8, MCK__93_ }, },
18477 { 5262 /* st2b */, AArch64::ST2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
19087 { 6111 /* tbl */, AArch64::TBL_ZZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorList281_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorList28, MCK_SVEVectorBReg }, },
20904 { 1029 /* ext */, AArch64::EXT_ZZI_B, Convert__SVEVectorBReg1_0__SVEVectorList281_1__Imm0_2551_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorList28, MCK_Imm0_255 }, },
22732 { 1978 /* ld2b */, AArch64::LD2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22733 { 1978 /* ld2b */, AArch64::LD2B, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64NoXZRshifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted8, MCK__93_ }, },
22734 { 1978 /* ld2b */, AArch64::LD2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s21_6, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
24773 { 4563 /* splice */, AArch64::SPLICE_ZPZZ_B, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorList281_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK_SVEVectorList28 }, },
25833 { 5262 /* st2b */, AArch64::ST2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
25834 { 5262 /* st2b */, AArch64::ST2B, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__GPR64NoXZRshifted81_4, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_GPR64NoXZRshifted8, MCK__93_ }, },
25835 { 5262 /* st2b */, AArch64::ST2B_IMM, Convert__SVEVectorList281_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s21_4, AMFBS_HasSVE, { MCK_SVEVectorList28, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s2, MCK_mul, MCK_vl, MCK__93_ }, },
26445 { 6111 /* tbl */, AArch64::TBL_ZZZZ_B, Convert__SVEVectorBReg1_0__SVEVectorList281_1__SVEVectorBReg1_2, AMFBS_HasSVE2, { MCK_SVEVectorBReg, MCK_SVEVectorList28, MCK_SVEVectorBReg }, },
29399 { 1029 /* ext */, 2 /* 1 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
29401 { 1029 /* ext */, 2 /* 1 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
32677 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
32679 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
32682 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
32685 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
32687 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
32689 { 1978 /* ld2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
36540 { 4563 /* splice */, 4 /* 2 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
36543 { 4563 /* splice */, 4 /* 2 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
38445 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
38447 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
38450 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
38453 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
38455 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
38457 { 5262 /* st2b */, 1 /* 0 */, MCK_SVEVectorList28, AMFBS_HasSVE },
39131 { 6111 /* tbl */, 2 /* 1 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
39133 { 6111 /* tbl */, 2 /* 1 */, MCK_SVEVectorList28, AMFBS_HasSVE2 },
40817 case MCK_SVEVectorList28: