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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10773 case MCK_SVEVectorAnyReg: {
12203 case MCK_SVEVectorAnyReg: return "MCK_SVEVectorAnyReg";
16167 { 2650 /* ldr */, AArch64::LDR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
16223 { 2650 /* ldr */, AArch64::LDR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm9, MCK_mul, MCK_vl, MCK__93_ }, },
16642 { 3375 /* movprfx */, AArch64::MOVPRFX_ZZ, Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK_SVEVectorAnyReg }, },
16642 { 3375 /* movprfx */, AArch64::MOVPRFX_ZZ, Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK_SVEVectorAnyReg }, },
18787 { 5598 /* str */, AArch64::STR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
18843 { 5598 /* str */, AArch64::STR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm9, MCK_mul, MCK_vl, MCK__93_ }, },
23525 { 2650 /* ldr */, AArch64::LDR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23581 { 2650 /* ldr */, AArch64::LDR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm9, MCK_mul, MCK_vl, MCK__93_ }, },
24000 { 3375 /* movprfx */, AArch64::MOVPRFX_ZZ, Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK_SVEVectorAnyReg }, },
24000 { 3375 /* movprfx */, AArch64::MOVPRFX_ZZ, Convert__SVEVectorAnyReg1_0__SVEVectorAnyReg1_1, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK_SVEVectorAnyReg }, },
26145 { 5598 /* str */, AArch64::STR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
26201 { 5598 /* str */, AArch64::STR_ZXI, Convert__SVEVectorAnyReg1_0__Reg1_2__SImm91_3, AMFBS_HasSVE, { MCK_SVEVectorAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm9, MCK_mul, MCK_vl, MCK__93_ }, },
34674 { 2650 /* ldr */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
34675 { 2650 /* ldr */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
34678 { 2650 /* ldr */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
34679 { 2650 /* ldr */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
35106 { 3375 /* movprfx */, 3 /* 0, 1 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
35107 { 3375 /* movprfx */, 3 /* 0, 1 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
38894 { 5598 /* str */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
38895 { 5598 /* str */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
38898 { 5598 /* str */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
38899 { 5598 /* str */, 1 /* 0 */, MCK_SVEVectorAnyReg, AMFBS_HasSVE },
40807 case MCK_SVEVectorAnyReg: