reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
10746 case MCK_SVEVector4bDReg: { 12200 case MCK_SVEVector4bDReg: return "MCK_SVEVector4bDReg"; 14244 { 1455 /* fmla */, AArch64::FMLA_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 14275 { 1487 /* fmls */, AArch64::FMLS_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 14354 { 1535 /* fmul */, AArch64::FMUL_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 16483 { 3343 /* mla */, AArch64::MLA_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 16500 { 3347 /* mls */, AArch64::MLS_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 16685 { 3410 /* mul */, AArch64::MUL_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 17567 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 17676 { 4808 /* sqrdmlah */, AArch64::SQRDMLAH_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 17695 { 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 17714 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 21607 { 1455 /* fmla */, AArch64::FMLA_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 21638 { 1487 /* fmls */, AArch64::FMLS_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 21717 { 1535 /* fmul */, AArch64::FMUL_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 23847 { 3343 /* mla */, AArch64::MLA_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 23864 { 3347 /* mls */, AArch64::MLS_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 24049 { 3410 /* mul */, AArch64::MUL_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 24929 { 4714 /* sqdmulh */, AArch64::SQDMULH_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 25038 { 4808 /* sqrdmlah */, AArch64::SQRDMLAH_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 25057 { 4817 /* sqrdmlsh */, AArch64::SQRDMLSH_ZZZI_D, Convert__SVEVectorDReg1_0__Tie0_1_1__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 25076 { 4826 /* sqrdmulh */, AArch64::SQRDMULH_ZZZI_D, Convert__SVEVectorDReg1_0__SVEVectorDReg1_1__SVEVector4bDReg1_2__IndexRange0_11_3, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SVEVector4bDReg, MCK_IndexRange0_1 }, }, 30290 { 1455 /* fmla */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 30292 { 1455 /* fmla */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 30334 { 1487 /* fmls */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 30336 { 1487 /* fmls */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 30460 { 1535 /* fmul */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 30462 { 1535 /* fmul */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE }, 34900 { 3343 /* mla */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 34902 { 3343 /* mla */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 34928 { 3347 /* mls */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 34930 { 3347 /* mls */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 35194 { 3410 /* mul */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 35196 { 3410 /* mul */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 36894 { 4714 /* sqdmulh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 36896 { 4714 /* sqdmulh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37128 { 4808 /* sqrdmlah */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37130 { 4808 /* sqrdmlah */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37148 { 4817 /* sqrdmlsh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37150 { 4817 /* sqrdmlsh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37168 { 4826 /* sqrdmulh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 37170 { 4826 /* sqrdmulh */, 4 /* 2 */, MCK_SVEVector4bDReg, AMFBS_HasSVE2 }, 40801 case MCK_SVEVector4bDReg: