reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
11093 case MCK_SVEExactFPImmOperandZeroOne: { 12245 case MCK_SVEExactFPImmOperandZeroOne: return "MCK_SVEExactFPImmOperandZeroOne"; 14127 { 1375 /* fmax */, AArch64::FMAX_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14129 { 1375 /* fmax */, AArch64::FMAX_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14131 { 1375 /* fmax */, AArch64::FMAX_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14141 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14143 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14145 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14189 { 1415 /* fmin */, AArch64::FMIN_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14191 { 1415 /* fmin */, AArch64::FMIN_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14193 { 1415 /* fmin */, AArch64::FMIN_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14203 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14205 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 14207 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21485 { 1375 /* fmax */, AArch64::FMAX_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21487 { 1375 /* fmax */, AArch64::FMAX_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21489 { 1375 /* fmax */, AArch64::FMAX_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21499 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21501 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21503 { 1380 /* fmaxnm */, AArch64::FMAXNM_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21547 { 1415 /* fmin */, AArch64::FMIN_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21549 { 1415 /* fmin */, AArch64::FMIN_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21551 { 1415 /* fmin */, AArch64::FMIN_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21561 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21563 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandZeroOne }, }, 21565 { 1420 /* fminnm */, AArch64::FMINNM_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandZeroOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandZeroOne }, }, 30072 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30075 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30082 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30085 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30092 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30095 { 1375 /* fmax */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30102 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30105 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30112 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30115 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30122 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30125 { 1380 /* fmaxnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30180 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30183 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30190 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30193 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30200 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30203 { 1415 /* fmin */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30210 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30213 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30220 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30223 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30230 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 30233 { 1420 /* fminnm */, 32 /* 5 */, MCK_SVEExactFPImmOperandZeroOne, AMFBS_HasSVE }, 40845 case MCK_SVEExactFPImmOperandZeroOne: