reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
11075 case MCK_SVEExactFPImmOperandHalfOne: { 12243 case MCK_SVEExactFPImmOperandHalfOne: return "MCK_SVEExactFPImmOperandHalfOne"; 13628 { 1072 /* fadd */, AArch64::FADD_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 13630 { 1072 /* fadd */, AArch64::FADD_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 13632 { 1072 /* fadd */, AArch64::FADD_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14598 { 1730 /* fsub */, AArch64::FSUB_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14600 { 1730 /* fsub */, AArch64::FSUB_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14602 { 1730 /* fsub */, AArch64::FSUB_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14604 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14606 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 14608 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 20986 { 1072 /* fadd */, AArch64::FADD_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 20988 { 1072 /* fadd */, AArch64::FADD_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 20990 { 1072 /* fadd */, AArch64::FADD_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21956 { 1730 /* fsub */, AArch64::FSUB_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21958 { 1730 /* fsub */, AArch64::FSUB_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21960 { 1730 /* fsub */, AArch64::FSUB_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21962 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorHReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21964 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorSReg, MCK_SVEExactFPImmOperandHalfOne }, }, 21966 { 1735 /* fsubr */, AArch64::FSUBR_ZPmI_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0_1_5__SVEExactFPImmOperandHalfOne1_5, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_SVEVectorDReg, MCK_SVEExactFPImmOperandHalfOne }, }, 29512 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 29515 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 29522 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 29525 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 29532 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 29535 { 1072 /* fadd */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30722 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30725 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30732 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30735 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30742 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30745 { 1730 /* fsub */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30752 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30755 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30762 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30765 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30772 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 30775 { 1735 /* fsubr */, 32 /* 5 */, MCK_SVEExactFPImmOperandHalfOne, AMFBS_HasSVE }, 40841 case MCK_SVEExactFPImmOperandHalfOne: