|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9599 case MCK_SVEAddSubImm8: {
12057 case MCK_SVEAddSubImm8: return "MCK_SVEAddSubImm8";
12721 { 25 /* add */, AArch64::ADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
17445 { 4576 /* sqadd */, AArch64::SQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
17863 { 5010 /* sqsub */, AArch64::SQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
18958 { 5924 /* sub */, AArch64::SUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
18994 { 5971 /* subr */, AArch64::SUBR_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
19492 { 6517 /* uqadd */, AArch64::UQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
19692 { 6687 /* uqsub */, AArch64::UQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
20079 { 25 /* add */, AArch64::ADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
24803 { 4576 /* sqadd */, AArch64::SQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
25221 { 5010 /* sqsub */, AArch64::SQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26316 { 5924 /* sub */, AArch64::SUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26352 { 5971 /* subr */, AArch64::SUBR_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
26850 { 6517 /* uqadd */, AArch64::UQADD_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
27050 { 6687 /* uqsub */, AArch64::UQSUB_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SVEAddSubImm82_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVEAddSubImm8 }, },
27678 { 25 /* add */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
27680 { 25 /* add */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
36594 { 4576 /* sqadd */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
36596 { 4576 /* sqadd */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
37382 { 5010 /* sqsub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
37384 { 5010 /* sqsub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
38938 { 5924 /* sub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
38940 { 5924 /* sub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
38996 { 5971 /* subr */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
38998 { 5971 /* subr */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
39752 { 6517 /* uqadd */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
39754 { 6517 /* uqadd */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
40124 { 6687 /* uqsub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
40126 { 6687 /* uqsub */, 4 /* 2 */, MCK_SVEAddSubImm8, AMFBS_HasSVE },
40705 case MCK_SVEAddSubImm8: