reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
9581 case MCK_SVEAddSubImm32: { 12055 case MCK_SVEAddSubImm32: return "MCK_SVEAddSubImm32"; 12717 { 25 /* add */, AArch64::ADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 17441 { 4576 /* sqadd */, AArch64::SQADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 17859 { 5010 /* sqsub */, AArch64::SQSUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 18954 { 5924 /* sub */, AArch64::SUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 18992 { 5971 /* subr */, AArch64::SUBR_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 19488 { 6517 /* uqadd */, AArch64::UQADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 19688 { 6687 /* uqsub */, AArch64::UQSUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 20075 { 25 /* add */, AArch64::ADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 24799 { 4576 /* sqadd */, AArch64::SQADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 25217 { 5010 /* sqsub */, AArch64::SQSUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 26312 { 5924 /* sub */, AArch64::SUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 26350 { 5971 /* subr */, AArch64::SUBR_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 26846 { 6517 /* uqadd */, AArch64::UQADD_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 27046 { 6687 /* uqsub */, AArch64::UQSUB_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SVEAddSubImm322_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVEAddSubImm32 }, }, 27666 { 25 /* add */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 27668 { 25 /* add */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 36582 { 4576 /* sqadd */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 36584 { 4576 /* sqadd */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 37370 { 5010 /* sqsub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 37372 { 5010 /* sqsub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 38926 { 5924 /* sub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 38928 { 5924 /* sub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 38988 { 5971 /* subr */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 38990 { 5971 /* subr */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 39740 { 6517 /* uqadd */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 39742 { 6517 /* uqadd */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 40112 { 6687 /* uqsub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 40114 { 6687 /* uqsub */, 4 /* 2 */, MCK_SVEAddSubImm32, AMFBS_HasSVE }, 40701 case MCK_SVEAddSubImm32: