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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9519 case MCK_SImm8: {
12047 case MCK_SImm8: return "MCK_SImm8";
16675 { 3410 /* mul */, AArch64::MUL_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
16677 { 3410 /* mul */, AArch64::MUL_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
16679 { 3410 /* mul */, AArch64::MUL_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
16681 { 3410 /* mul */, AArch64::MUL_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },
17268 { 4419 /* smax */, AArch64::SMAX_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
17269 { 4419 /* smax */, AArch64::SMAX_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
17270 { 4419 /* smax */, AArch64::SMAX_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
17271 { 4419 /* smax */, AArch64::SMAX_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },
17302 { 4440 /* smin */, AArch64::SMIN_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
17303 { 4440 /* smin */, AArch64::SMIN_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
17304 { 4440 /* smin */, AArch64::SMIN_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
17305 { 4440 /* smin */, AArch64::SMIN_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },
24033 { 3410 /* mul */, AArch64::MUL_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
24035 { 3410 /* mul */, AArch64::MUL_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
24037 { 3410 /* mul */, AArch64::MUL_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
24039 { 3410 /* mul */, AArch64::MUL_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },
24626 { 4419 /* smax */, AArch64::SMAX_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
24627 { 4419 /* smax */, AArch64::SMAX_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
24628 { 4419 /* smax */, AArch64::SMAX_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
24629 { 4419 /* smax */, AArch64::SMAX_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },
24660 { 4440 /* smin */, AArch64::SMIN_ZI_H, Convert__SVEVectorHReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SImm8 }, },
24661 { 4440 /* smin */, AArch64::SMIN_ZI_S, Convert__SVEVectorSReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SImm8 }, },
24662 { 4440 /* smin */, AArch64::SMIN_ZI_D, Convert__SVEVectorDReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_SImm8 }, },
24663 { 4440 /* smin */, AArch64::SMIN_ZI_B, Convert__SVEVectorBReg1_0__Tie0_1_2__SImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SImm8 }, },