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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9456 case MCK_SImm4s4: {
12040 case MCK_SImm4s4: return "MCK_SImm4s4";
15628 { 2036 /* ld4b */, AArch64::LD4B_IMM, Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList48, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
15631 { 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList464, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
15634 { 2046 /* ld4h */, AArch64::LD4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList416, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
15685 { 2056 /* ld4w */, AArch64::LD4W_IMM, Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList432, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
18637 { 5315 /* st4b */, AArch64::ST4B_IMM, Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList48, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
18640 { 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList464, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
18643 { 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList416, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
18646 { 5330 /* st4w */, AArch64::ST4W_IMM, Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList432, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
22986 { 2036 /* ld4b */, AArch64::LD4B_IMM, Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList48, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
22989 { 2041 /* ld4d */, AArch64::LD4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList464, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
22992 { 2046 /* ld4h */, AArch64::LD4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList416, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
23043 { 2056 /* ld4w */, AArch64::LD4W_IMM, Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s41_6, AMFBS_HasSVE, { MCK_SVEVectorList432, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
25995 { 5315 /* st4b */, AArch64::ST4B_IMM, Convert__SVEVectorList481_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList48, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
25998 { 5320 /* st4d */, AArch64::ST4D_IMM, Convert__SVEVectorList4641_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList464, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
26001 { 5325 /* st4h */, AArch64::ST4H_IMM, Convert__SVEVectorList4161_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList416, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },
26004 { 5330 /* st4w */, AArch64::ST4W_IMM, Convert__SVEVectorList4321_0__SVEPredicate3bAnyReg1_1__Reg1_3__SImm4s41_4, AMFBS_HasSVE, { MCK_SVEVectorList432, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_GPR64sp, MCK_SImm4s4, MCK_mul, MCK_vl, MCK__93_ }, },