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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9420 case MCK_SImm4s16: {
12036 case MCK_SImm4s16: return "MCK_SImm4s16";
15117 { 1896 /* ld1rqb */, AArch64::LD1RQ_B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15119 { 1896 /* ld1rqb */, AArch64::LD1RQ_B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15123 { 1903 /* ld1rqd */, AArch64::LD1RQ_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15125 { 1903 /* ld1rqd */, AArch64::LD1RQ_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15129 { 1910 /* ld1rqh */, AArch64::LD1RQ_H_IMM, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15131 { 1910 /* ld1rqh */, AArch64::LD1RQ_H_IMM, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15135 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15137 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22475 { 1896 /* ld1rqb */, AArch64::LD1RQ_B_IMM, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22477 { 1896 /* ld1rqb */, AArch64::LD1RQ_B_IMM, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22481 { 1903 /* ld1rqd */, AArch64::LD1RQ_D_IMM, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22483 { 1903 /* ld1rqd */, AArch64::LD1RQ_D_IMM, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22487 { 1910 /* ld1rqh */, AArch64::LD1RQ_H_IMM, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22489 { 1910 /* ld1rqh */, AArch64::LD1RQ_H_IMM, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList116, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22493 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22495 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },