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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 9146 case MCK_LogicalImm64: {
12004 case MCK_LogicalImm64: return "MCK_LogicalImm64";
12813 { 120 /* and */, AArch64::ANDXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
12818 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
12834 { 124 /* ands */, AArch64::ANDSXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_LogicalImm64 }, },
13491 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
13506 { 975 /* eor */, AArch64::EORXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
13511 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
16536 { 3356 /* mov */, AArch64::ORRXri, Convert__Reg1_0__regXZR__LogicalImm641_1, AMFBS_None, { MCK_GPR64sp, MCK_LogicalImm64 }, },
16781 { 3495 /* orr */, AArch64::ORRXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
16790 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
19166 { 6158 /* tst */, AArch64::ANDSXri, Convert__regXZR__Reg1_0__LogicalImm641_1, AMFBS_None, { MCK_GPR64, MCK_LogicalImm64 }, },
20171 { 120 /* and */, AArch64::ANDXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
20176 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
20192 { 124 /* ands */, AArch64::ANDSXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_LogicalImm64 }, },
20849 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
20864 { 975 /* eor */, AArch64::EORXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
20869 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
23894 { 3356 /* mov */, AArch64::ORRXri, Convert__Reg1_0__regXZR__LogicalImm641_1, AMFBS_None, { MCK_GPR64sp, MCK_LogicalImm64 }, },
24139 { 3495 /* orr */, AArch64::ORRXri, Convert__Reg1_0__Reg1_1__LogicalImm641_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64, MCK_LogicalImm64 }, },
24148 { 3495 /* orr */, AArch64::ORR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
26524 { 6158 /* tst */, AArch64::ANDSXri, Convert__regXZR__Reg1_0__LogicalImm641_1, AMFBS_None, { MCK_GPR64, MCK_LogicalImm64 }, },