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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc10973 case MCK_Imm0_65535: {
12231 case MCK_Imm0_65535: return "MCK_Imm0_65535";
12965 { 363 /* brk */, AArch64::BRK, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
13419 { 906 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
13421 { 912 /* dcps2 */, AArch64::DCPS2, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
13423 { 918 /* dcps3 */, AArch64::DCPS3, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
14623 { 1786 /* hlt */, AArch64::HLT, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
14624 { 1790 /* hvc */, AArch64::HVC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
16624 { 3365 /* movk */, AArch64::MOVKWi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
16629 { 3365 /* movk */, AArch64::MOVKXi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
16630 { 3365 /* movk */, AArch64::MOVKWi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
16631 { 3365 /* movk */, AArch64::MOVKXi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
16634 { 3370 /* movn */, AArch64::MOVNWi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
16639 { 3370 /* movn */, AArch64::MOVNXi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
16640 { 3370 /* movn */, AArch64::MOVNWi, Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
16641 { 3370 /* movn */, AArch64::MOVNXi, Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
16655 { 3388 /* movz */, AArch64::MOVZWi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
16660 { 3388 /* movz */, AArch64::MOVZXi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
16661 { 3388 /* movz */, AArch64::MOVZWi, Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
16662 { 3388 /* movz */, AArch64::MOVZXi, Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
17301 { 4436 /* smc */, AArch64::SMC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
19033 { 6004 /* svc */, AArch64::SVC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
19130 { 6128 /* tcancel */, AArch64::TCANCEL, Convert__Imm0_655351_0, AMFBS_HasTME, { MCK_Imm0_65535 }, },
19300 { 6331 /* udf */, AArch64::UDF, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
20323 { 363 /* brk */, AArch64::BRK, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
20777 { 906 /* dcps1 */, AArch64::DCPS1, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
20779 { 912 /* dcps2 */, AArch64::DCPS2, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
20781 { 918 /* dcps3 */, AArch64::DCPS3, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
21981 { 1786 /* hlt */, AArch64::HLT, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
21982 { 1790 /* hvc */, AArch64::HVC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
23982 { 3365 /* movk */, AArch64::MOVKWi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
23987 { 3365 /* movk */, AArch64::MOVKXi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
23988 { 3365 /* movk */, AArch64::MOVKWi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
23989 { 3365 /* movk */, AArch64::MOVKXi, Convert__Reg1_0__Tie0_1_1__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
23992 { 3370 /* movn */, AArch64::MOVNWi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
23997 { 3370 /* movn */, AArch64::MOVNXi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
23998 { 3370 /* movn */, AArch64::MOVNWi, Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
23999 { 3370 /* movn */, AArch64::MOVNXi, Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
24013 { 3388 /* movz */, AArch64::MOVZWi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535 }, },
24018 { 3388 /* movz */, AArch64::MOVZXi, Convert__Reg1_0__Imm0_655351_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535 }, },
24019 { 3388 /* movz */, AArch64::MOVZWi, Convert__Reg1_0__Imm0_655351_1__MovImm32Shifter1_2, AMFBS_None, { MCK_GPR32, MCK_Imm0_65535, MCK_MovImm32Shifter }, },
24020 { 3388 /* movz */, AArch64::MOVZXi, Convert__Reg1_0__Imm0_655351_1__MovImm64Shifter1_2, AMFBS_None, { MCK_GPR64, MCK_Imm0_65535, MCK_MovImm64Shifter }, },
24659 { 4436 /* smc */, AArch64::SMC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
26391 { 6004 /* svc */, AArch64::SVC, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },
26488 { 6128 /* tcancel */, AArch64::TCANCEL, Convert__Imm0_655351_0, AMFBS_HasTME, { MCK_Imm0_65535 }, },
26658 { 6331 /* udf */, AArch64::UDF, Convert__Imm0_655351_0, AMFBS_None, { MCK_Imm0_65535 }, },