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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8979 case MCK_GPR64shifted32: {
11985 case MCK_GPR64shifted32: return "MCK_GPR64shifted32";
15930 { 2487 /* ldff1sw */, AArch64::LDFF1SW_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15938 { 2487 /* ldff1sw */, AArch64::LDFF1SW_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15954 { 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15960 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15968 { 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15974 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23288 { 2487 /* ldff1sw */, AArch64::LDFF1SW_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23296 { 2487 /* ldff1sw */, AArch64::LDFF1SW_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23312 { 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23318 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23326 { 2495 /* ldff1w */, AArch64::LDFF1W_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23332 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
33762 { 2487 /* ldff1sw */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33765 { 2487 /* ldff1sw */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33808 { 2487 /* ldff1sw */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33811 { 2487 /* ldff1sw */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33892 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33895 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33926 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33929 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33972 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
33975 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
34008 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
34011 { 2495 /* ldff1w */, 64 /* 6 */, MCK_GPR64shifted32, AMFBS_HasSVE },
40663 case MCK_GPR64shifted32: