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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8060 case MCK_GPR32sponly:
11222 case AArch64::WSP: OpKind = MCK_GPR32sponly; break;
11859 case MCK_GPR32sponly: return "MCK_GPR32sponly";
12704 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
12708 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
12765 { 72 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32, MCK_GPR32sponly, MCK_GPR32 }, },
13202 { 661 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32 }, },
13215 { 665 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32 }, },
16517 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
16524 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
18941 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
18945 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
18999 { 5976 /* subs */, AArch64::SUBSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32, MCK_GPR32sponly, MCK_GPR32 }, },
20062 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
20066 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
20123 { 72 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32, MCK_GPR32sponly, MCK_GPR32 }, },
20560 { 661 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32 }, },
20573 { 665 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32 }, },
23875 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
23882 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
26299 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
26303 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
26357 { 5976 /* subs */, AArch64::SUBSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32, MCK_GPR32sponly, MCK_GPR32 }, },