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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8063 case MCK_GPR32sp: return true;
8368 case MCK_GPR32sp: return true;
8731 case MCK_GPR32sp: return true;
8746 case MCK_GPR32sp:
11953 case MCK_GPR32sp: return "MCK_GPR32sp";
12704 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
12708 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
12709 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
12709 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
12710 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
12710 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
12724 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
12724 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
12767 { 72 /* adds */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
12768 { 72 /* adds */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
12774 { 72 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
12811 { 120 /* and */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
12915 { 288 /* bic */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
13205 { 661 /* cmn */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
13206 { 661 /* cmn */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
13211 { 661 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
13218 { 665 /* cmp */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
13219 { 665 /* cmp */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
13224 { 665 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
13378 { 787 /* cpy */, AArch64::CPY_ZPmR_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
13382 { 787 /* cpy */, AArch64::CPY_ZPmR_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
13390 { 787 /* cpy */, AArch64::CPY_ZPmR_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
13458 { 962 /* dup */, AArch64::DUP_ZR_H, Convert__SVEVectorHReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_GPR32sp }, },
13460 { 962 /* dup */, AArch64::DUP_ZR_S, Convert__SVEVectorSReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_GPR32sp }, },
13464 { 962 /* dup */, AArch64::DUP_ZR_B, Convert__SVEVectorBReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_GPR32sp }, },
13494 { 971 /* eon */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
13504 { 975 /* eor */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
16517 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
16524 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
16525 { 3356 /* mov */, AArch64::ORRWri, Convert__Reg1_0__regWZR__LogicalImm321_1, AMFBS_None, { MCK_GPR32sp, MCK_LogicalImm32 }, },
16539 { 3356 /* mov */, AArch64::DUP_ZR_H, Convert__SVEVectorHReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_GPR32sp }, },
16543 { 3356 /* mov */, AArch64::DUP_ZR_S, Convert__SVEVectorSReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_GPR32sp }, },
16552 { 3356 /* mov */, AArch64::DUP_ZR_B, Convert__SVEVectorBReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_GPR32sp }, },
16581 { 3356 /* mov */, AArch64::CPY_ZPmR_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
16586 { 3356 /* mov */, AArch64::CPY_ZPmR_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
16596 { 3356 /* mov */, AArch64::CPY_ZPmR_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
16761 { 3486 /* orn */, AArch64::ORRWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
16779 { 3495 /* orr */, AArch64::ORRWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
18941 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
18945 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
18946 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
18946 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
18947 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
18947 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
18961 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
18961 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
19001 { 5976 /* subs */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
19002 { 5976 /* subs */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
19008 { 5976 /* subs */, AArch64::SUBSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20062 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
20066 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
20067 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20067 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20068 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
20068 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
20089 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20089 { 25 /* add */, AArch64::ADDWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20125 { 72 /* adds */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20126 { 72 /* adds */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
20132 { 72 /* adds */, AArch64::ADDSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20169 { 120 /* and */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
20273 { 288 /* bic */, AArch64::ANDWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
20563 { 661 /* cmn */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
20564 { 661 /* cmn */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
20569 { 661 /* cmn */, AArch64::ADDSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20576 { 665 /* cmp */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
20577 { 665 /* cmp */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
20582 { 665 /* cmp */, AArch64::SUBSWrx, Convert__regWZR__Reg1_0__Reg1_1__Extend1_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
20736 { 787 /* cpy */, AArch64::CPY_ZPmR_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
20740 { 787 /* cpy */, AArch64::CPY_ZPmR_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
20748 { 787 /* cpy */, AArch64::CPY_ZPmR_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
20816 { 962 /* dup */, AArch64::DUP_ZR_H, Convert__SVEVectorHReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_GPR32sp }, },
20818 { 962 /* dup */, AArch64::DUP_ZR_S, Convert__SVEVectorSReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_GPR32sp }, },
20822 { 962 /* dup */, AArch64::DUP_ZR_B, Convert__SVEVectorBReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_GPR32sp }, },
20852 { 971 /* eon */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
20862 { 975 /* eor */, AArch64::EORWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
23875 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp }, },
23882 { 3356 /* mov */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__imm_95_0__imm_95_0, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly }, },
23883 { 3356 /* mov */, AArch64::ORRWri, Convert__Reg1_0__regWZR__LogicalImm321_1, AMFBS_None, { MCK_GPR32sp, MCK_LogicalImm32 }, },
23897 { 3356 /* mov */, AArch64::DUP_ZR_H, Convert__SVEVectorHReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_GPR32sp }, },
23901 { 3356 /* mov */, AArch64::DUP_ZR_S, Convert__SVEVectorSReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_GPR32sp }, },
23910 { 3356 /* mov */, AArch64::DUP_ZR_B, Convert__SVEVectorBReg1_0__Reg1_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_GPR32sp }, },
23943 { 3356 /* mov */, AArch64::CPY_ZPmR_H, Convert__SVEVectorHReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
23948 { 3356 /* mov */, AArch64::CPY_ZPmR_S, Convert__SVEVectorSReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
23958 { 3356 /* mov */, AArch64::CPY_ZPmR_B, Convert__SVEVectorBReg1_0__Tie0_1_1__SVEPredicate3bAnyReg1_1__Reg1_4, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_m, MCK_GPR32sp }, },
24119 { 3486 /* orn */, AArch64::ORRWri, Convert__Reg1_0__Reg1_1__LogicalImm32Not1_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32Not }, },
24137 { 3495 /* orr */, AArch64::ORRWri, Convert__Reg1_0__Reg1_1__LogicalImm321_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32, MCK_LogicalImm32 }, },
26299 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sponly, MCK_GPR32sp, MCK_GPR32 }, },
26303 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_16, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sponly, MCK_GPR32 }, },
26304 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
26304 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
26305 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
26305 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
26326 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
26326 { 5924 /* sub */, AArch64::SUBWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },
26359 { 5976 /* subs */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
26360 { 5976 /* subs */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
26366 { 5976 /* subs */, AArch64::SUBSWrx, Convert__Reg1_0__Reg1_1__Reg1_2__Extend1_3, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_GPR32, MCK_Extend }, },