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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8807 case MCK_AddSubImmNeg: {
11965 case MCK_AddSubImmNeg: return "MCK_AddSubImmNeg";
12709 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
12713 { 25 /* add */, AArch64::SUBXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
12767 { 72 /* adds */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
12771 { 72 /* adds */, AArch64::SUBSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
13205 { 661 /* cmn */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
13208 { 661 /* cmn */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
13218 { 665 /* cmp */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
13221 { 665 /* cmp */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
18946 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
18950 { 5924 /* sub */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
19001 { 5976 /* subs */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
19005 { 5976 /* subs */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
20067 { 25 /* add */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20071 { 25 /* add */, AArch64::SUBXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
20125 { 72 /* adds */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
20129 { 72 /* adds */, AArch64::SUBSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
20563 { 661 /* cmn */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
20566 { 661 /* cmn */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
20576 { 665 /* cmp */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_AddSubImmNeg }, },
20579 { 665 /* cmp */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImmNeg2_1, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_AddSubImmNeg }, },
26304 { 5924 /* sub */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImmNeg }, },
26308 { 5924 /* sub */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImmNeg }, },
26359 { 5976 /* subs */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImmNeg }, },
26363 { 5976 /* subs */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImmNeg2_2, AMFBS_UseNegativeImmediates, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImmNeg }, },
27652 { 25 /* add */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27653 { 25 /* add */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27656 { 25 /* add */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27657 { 25 /* add */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27740 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27741 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27744 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
27745 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28298 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28299 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28302 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28303 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28306 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28307 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28310 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
28311 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
38912 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
38913 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
38916 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
38917 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
39016 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
39017 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
39020 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
39021 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImmNeg, AMFBS_UseNegativeImmediates },
40635 case MCK_AddSubImmNeg: