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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 8816 case MCK_AddSubImm: {
11966 case MCK_AddSubImm: return "MCK_AddSubImm";
12710 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
12714 { 25 /* add */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
12768 { 72 /* adds */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
12772 { 72 /* adds */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
13206 { 661 /* cmn */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
13209 { 661 /* cmn */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
13219 { 665 /* cmp */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
13222 { 665 /* cmp */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
18947 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
18951 { 5924 /* sub */, AArch64::SUBXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
19002 { 5976 /* subs */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
19006 { 5976 /* subs */, AArch64::SUBSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
20068 { 25 /* add */, AArch64::ADDWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
20072 { 25 /* add */, AArch64::ADDXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
20126 { 72 /* adds */, AArch64::ADDSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
20130 { 72 /* adds */, AArch64::ADDSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
20564 { 661 /* cmn */, AArch64::ADDSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
20567 { 661 /* cmn */, AArch64::ADDSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
20577 { 665 /* cmp */, AArch64::SUBSWri, Convert__regWZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR32sp, MCK_AddSubImm }, },
20580 { 665 /* cmp */, AArch64::SUBSXri, Convert__regXZR__Reg1_0__AddSubImm2_1, AMFBS_None, { MCK_GPR64sp, MCK_AddSubImm }, },
26305 { 5924 /* sub */, AArch64::SUBWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32sp, MCK_GPR32sp, MCK_AddSubImm }, },
26309 { 5924 /* sub */, AArch64::SUBXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64sp, MCK_GPR64sp, MCK_AddSubImm }, },
26360 { 5976 /* subs */, AArch64::SUBSWri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR32, MCK_GPR32sp, MCK_AddSubImm }, },
26364 { 5976 /* subs */, AArch64::SUBSXri, Convert__Reg1_0__Reg1_1__AddSubImm2_2, AMFBS_None, { MCK_GPR64, MCK_GPR64sp, MCK_AddSubImm }, },
27654 { 25 /* add */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27655 { 25 /* add */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27658 { 25 /* add */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27659 { 25 /* add */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27742 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27743 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27746 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
27747 { 72 /* adds */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
28300 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28301 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28304 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28305 { 661 /* cmn */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28308 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28309 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28312 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
28313 { 665 /* cmp */, 2 /* 1 */, MCK_AddSubImm, AMFBS_None },
38914 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
38915 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
38918 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
38919 { 5924 /* sub */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
39018 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
39019 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
39022 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
39023 { 5976 /* subs */, 4 /* 2 */, MCK_AddSubImm, AMFBS_None },
40637 case MCK_AddSubImm: