reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
21612 { 1455 /* fmla */, AArch64::FMLAv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 21643 { 1487 /* fmls */, AArch64::FMLSv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON_HasFullFP16, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 23851 { 3343 /* mla */, AArch64::MLAv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 23868 { 3347 /* mls */, AArch64::MLSv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 24702 { 4463 /* smlal2 */, AArch64::SMLALv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 24722 { 4490 /* smlsl2 */, AArch64::SMLSLv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 24878 { 4632 /* sqdmlal2 */, AArch64::SQDMLALv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 24903 { 4677 /* sqdmlsl2 */, AArch64::SQDMLSLv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 25042 { 4808 /* sqrdmlah */, AArch64::SQRDMLAHv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON_HasRDM, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 25061 { 4817 /* sqrdmlsh */, AArch64::SQRDMLSHv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON_HasRDM, { MCK__DOT_8h, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 26773 { 6417 /* umlal2 */, AArch64::UMLALv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, }, 26793 { 6444 /* umlsl2 */, AArch64::UMLSLv8i16_indexed, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__VectorRegLo1_3__IndexRange0_71_4, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_VectorRegLo, MCK_IndexRange0_7 }, },