reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
24354 { 3876 /* rshrn2 */, AArch64::RSHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 24580 { 4305 /* shrn2 */, AArch64::SHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25109 { 4858 /* sqrshrn2 */, AArch64::SQRSHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25124 { 4894 /* sqrshrun2 */, AArch64::SQRSHRUNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25188 { 4951 /* sqshrn2 */, AArch64::SQSHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25203 { 4983 /* sqshrun2 */, AArch64::SQSHRUNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25287 { 5088 /* sri */, AArch64::SRIv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25327 { 5111 /* srsra */, AArch64::SRSRAv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 25368 { 5159 /* ssra */, AArch64::SSRAv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 26983 { 6616 /* uqrshrn2 */, AArch64::UQRSHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 27032 { 6663 /* uqshrn2 */, AArch64::UQSHRNv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 27135 { 6768 /* ursra */, AArch64::URSRAv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, }, 27190 { 6818 /* usra */, AArch64::USRAv4i32_shift, Convert__VectorReg1281_1__Tie0_2_2__VectorReg1281_2__Imm1_321_3, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VectorReg128, MCK_VectorReg128, MCK_Imm1_32 }, },