reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
13163   { 641 /* cmle */, AArch64::CMGEv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
13164   { 641 /* cmle */, AArch64::CMGEv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13165   { 641 /* cmle */, AArch64::CMGEv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13166   { 641 /* cmle */, AArch64::CMGEv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13171   { 646 /* cmlo */, AArch64::CMHIv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
13172   { 646 /* cmlo */, AArch64::CMHIv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13173   { 646 /* cmlo */, AArch64::CMHIv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13174   { 646 /* cmlo */, AArch64::CMHIv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13179   { 651 /* cmls */, AArch64::CMHSv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
13180   { 651 /* cmls */, AArch64::CMHSv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13181   { 651 /* cmls */, AArch64::CMHSv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13182   { 651 /* cmls */, AArch64::CMHSv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13195   { 656 /* cmlt */, AArch64::CMGTv16i8, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b }, },
13196   { 656 /* cmlt */, AArch64::CMGTv2i64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13197   { 656 /* cmlt */, AArch64::CMGTv4i32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13198   { 656 /* cmlt */, AArch64::CMGTv8i16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13601   { 1060 /* facle */, AArch64::FACGEv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13602   { 1060 /* facle */, AArch64::FACGEv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13603   { 1060 /* facle */, AArch64::FACGEv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_HasNEON_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13611   { 1066 /* faclt */, AArch64::FACGTv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13612   { 1066 /* faclt */, AArch64::FACGTv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13613   { 1066 /* faclt */, AArch64::FACGTv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_HasNEON_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13804   { 1138 /* fcmle */, AArch64::FCMGEv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13806   { 1138 /* fcmle */, AArch64::FCMGEv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13808   { 1138 /* fcmle */, AArch64::FCMGEv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_HasNEON_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },
13838   { 1144 /* fcmlt */, AArch64::FCMGTv2f64, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d, MCK_VectorReg128, MCK__DOT_2d }, },
13840   { 1144 /* fcmlt */, AArch64::FCMGTv4f32, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_None, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s }, },
13842   { 1144 /* fcmlt */, AArch64::FCMGTv8f16, Convert__VectorReg1281_0__VectorReg1281_4__VectorReg1281_2, AMFBS_HasNEON_HasFullFP16, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h }, },