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reference to multiple definitions → definitions
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References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
16995   { 3876 /* rshrn2 */, AArch64::RSHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17221   { 4305 /* shrn2 */, AArch64::SHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17750   { 4858 /* sqrshrn2 */, AArch64::SQRSHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17765   { 4894 /* sqrshrun2 */, AArch64::SQRSHRUNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17829   { 4951 /* sqshrn2 */, AArch64::SQSHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17844   { 4983 /* sqshrun2 */, AArch64::SQSHRUNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
17925   { 5088 /* sri */, AArch64::SRIv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm1_8 }, },
17965   { 5111 /* srsra */, AArch64::SRSRAv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm1_8 }, },
18006   { 5159 /* ssra */, AArch64::SSRAv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm1_8 }, },
19624   { 6616 /* uqrshrn2 */, AArch64::UQRSHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
19673   { 6663 /* uqshrn2 */, AArch64::UQSHRNv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_8 }, },
19773   { 6768 /* ursra */, AArch64::URSRAv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm1_8 }, },
19828   { 6818 /* usra */, AArch64::USRAv16i8_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_81_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_16b, MCK_VectorReg128, MCK__DOT_16b, MCK_Imm1_8 }, },