reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
16996 { 3876 /* rshrn2 */, AArch64::RSHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17222 { 4305 /* shrn2 */, AArch64::SHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17751 { 4858 /* sqrshrn2 */, AArch64::SQRSHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17766 { 4894 /* sqrshrun2 */, AArch64::SQRSHRUNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17830 { 4951 /* sqshrn2 */, AArch64::SQSHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17845 { 4983 /* sqshrun2 */, AArch64::SQSHRUNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 17927 { 5088 /* sri */, AArch64::SRIv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, }, 17967 { 5111 /* srsra */, AArch64::SRSRAv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, }, 18008 { 5159 /* ssra */, AArch64::SSRAv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, }, 19625 { 6616 /* uqrshrn2 */, AArch64::UQRSHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 19674 { 6663 /* uqshrn2 */, AArch64::UQSHRNv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_2d, MCK_Imm1_32 }, }, 19775 { 6768 /* ursra */, AArch64::URSRAv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, }, 19830 { 6818 /* usra */, AArch64::USRAv4i32_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_321_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_4s, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_32 }, },