reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
16997   { 3876 /* rshrn2 */, AArch64::RSHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17223   { 4305 /* shrn2 */, AArch64::SHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17752   { 4858 /* sqrshrn2 */, AArch64::SQRSHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17767   { 4894 /* sqrshrun2 */, AArch64::SQRSHRUNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17831   { 4951 /* sqshrn2 */, AArch64::SQSHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17846   { 4983 /* sqshrun2 */, AArch64::SQSHRUNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
17928   { 5088 /* sri */, AArch64::SRIv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
17968   { 5111 /* srsra */, AArch64::SRSRAv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
18009   { 5159 /* ssra */, AArch64::SSRAv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
19626   { 6616 /* uqrshrn2 */, AArch64::UQRSHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
19675   { 6663 /* uqshrn2 */, AArch64::UQSHRNv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_4s, MCK_Imm1_16 }, },
19776   { 6768 /* ursra */, AArch64::URSRAv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },
19831   { 6818 /* usra */, AArch64::USRAv8i16_shift, Convert__VectorReg1281_0__Tie0_1_1__VectorReg1281_2__Imm1_161_4, AMFBS_HasNEON, { MCK_VectorReg128, MCK__DOT_8h, MCK_VectorReg128, MCK__DOT_8h, MCK_Imm1_16 }, },